SPIE Lithography Asia 2008

Daejin Park a, Jinyoung Choi a, Hyoungsoon Yune a, Jaeseung Choi a, Cheolkyun Kim a, Bong-Ryoul Choi b and Donggyu Yim a

a R&D Division, Hynix Semiconductor Inc.

San 136-1, Ami-ri, Bubal-eub, Ichon-si, Kyungki-do 467-701, Korea
Tel : 82-31-630-1271, Fax : 82-31-630-4548, E-mail : daejin1.park@hynix.com

b ASML Korea Co., Ltd


Recently, the dramatic acceleration in dimensional shrink of DRAM memory devices has been observed. For sub 60 nm memory device, we suggest the following method of optical proximity correction (OPC) to enhance the critical dimension uniformity (CDU). In order to enhance CD variation of each transistor, hundreds of thousand transistor CD data were used through design based metrology (DBM) system. In a traditional OPC modeling method, it is difficult to realize enhancement of CD variation on chip because of the limitation of OPC feedback data.

Even though optical properties are surely understood from recent computational lithography models, there are so many abnormalities like mask effect, thermal effect from the wafer process, and etch bias variation of the etching process. Especially, etch bias is too complicate to predict since it is related to variations such as space among adjacent patterns, the density of neighboring patterns and so on.

In this paper, process proximity correction (PPC) adopting the pattern to pattern matching method is used with huge amount of CD data from real wafer. This is the method which corrects CD bias with respect to each pattern by matching the same coordinates. New PPC method for enhancement of full chip CD variation is proposed which automatically corrects off-targeted feature by using full chip CD measurement data of DBM system. Thus, gate CDU of sub 60 nm node is reduced by using new PPC method. Analysis showed that our novel PPC method enhanced CD variation of full chip up to 20 percent.