SPIE 2008

Jeong-Geun Park*a, Sang-ho Lee*a, Young-Seog Kang*a, Young-Kyou Park*a Tadashi Kitamura*b, Toshiaki Hasebe*b, Shinichi Nakazawa*b

aFAB Equipment Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co.Ltd.

bNGR Inc., Tokyo, Japan 174-0051

ABSTRACT

As the design technology node becomes smaller, k1 factor is decreasing below 0.3 and optical proximity correction (OPC) divergence is increasing. The gate critical dimension (CD) control and systematic defect inspection is becoming critical to improving circuit yield. For more accurate OPC verification and systematic defect inspection, design based metrology become increasingly important, because accuracy of simulation based OPC model verification has its limitation. In this paper, we used NGR-2100 as a design based metrology tool to confirm the accuracy of OPC modeling and process window qualification. NGR-2100 uses high energy wide-beam for high speed secondary electron sampling and large field of view. It can measure full chip CD distribution and more accurate process window compared to optical inspection tool. Because of using high energy beam, conducting layer like carbon film should be coated on photo resist patterned sample wafer to prevent local electron charging. However, coated carbon may increase CD variation. By using atomic layer deposition-type TiN layer instead of carbon, CD variation could be reduced.

Keywords: Design Based Metrology, NGR2100, OPC Model, PWQ, Carbon Coating, Local Charge Up, TiN