Hyunjo Yang *a, Jungchan Kim a, Taehyeong Lee a, Areum Jung a, Gyun Yoo a, Donggyu Yim a, Sungki Park a, Toshiaki Hasebe b, Masahiro Yamamoto b, Jun Cai c
a Research & Development Division, Hynix Semiconductor Inc., Korea
b NGR Inc., Japan
c Anchor Semiconductor, Inc., USA
Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The major applications of DBM are OPC accuracy improvement, DFM feed-back through Process Window Qualification (PWQ) and advanced process control. In general, however, the amount of output data from DBM is normally so large that it is very hard to handle the data for valuable feed-back. In case of PWQ, more than thousands of hot spots are detected on a single chip at the edge of process window. So, it takes much time and labor to review and analyze all the hot spots detected at PWQ. Design-related systematic defects, however, will be found repeatedly and if they can be classified into groups, it would be possible to save a lot of time for the analysis.
We have demonstrated an EDA tool which can handle the large amount of output data from DBM by reducing pattern defects to groups. It can classify millions of patterns into less than thousands of pattern groups. It has been evaluated on the analysis of PWQ of metal layer in NAND Flash memory device and random contact hole patterns in a DRAM device.
The result shows that this EDA tool can handle the CD measurement data easily and can save us a lot of time and labor for the analysis. The procedures of systematic defect filtering and data handling using an EDA tool are presented in detail.
Key words: Design Based Metrology, EDA tool, Systematic defect filtering