- Arthur:Minyoung Shim
- Company:Samsung Electronics
Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer. Especially, patterning bridge and misaligned contact failures between two layers are so difficult to verify
during the process inside fabrication line. For that reason, until now, we carry out electrical measurements and examine vertical structures using VSEM(Vertical SEM) on fab-out wafers. However, it requires a pretty long time to analyze the process after fab-out and importantly, we are not able to
obtain reliable amount data due to limited sampling points. Also, in case of VSEM, it is a destructive examining process.
In order to overcome the difficulties of the problems mentioned above, we have developed the interlayer design verification methodology using contour image. Our methodology is comprised of 4-steps: preparation, measurement, data-processing, and design verification. In the 1st step,preparation, we define measured regions(or points) and prepare GDSII file for measured patterns. It is very important since it affects measurement step and design verification step. The 2nd step, measurement, is measuring the patterns of wafers. After measuring of patterns, we extract the contour images of the measured patterns using NGR (Nano Geometry Research) equipment. The 3rd step, data-processing, is to overlap each measured contour images onto the intended layout designs. Through this process,
we are now able to extract the relation (like overlap, space, etc.) between interlayer. We use our in-house developed tool to merge images and to extract data. (Fig. 1) The 4th step, design verification, is to analyze the extracted relation (overlap, space, etc.) and verify the interlayer designs. A large amount of data can be collected and shows normal distributions which enable us to analyze the data statistically. We verify the interlayer design by specific criteria. (Fig. 2) The criteria is determined by fabrication, electrical characteristic, and other elements. Through this verification, we check on the margin of current interlayer design and give feedback on weak points and the amount of deficiency. (Fig. 3) Our methodology makes it possible to verify interlayer design by extracting the contour image from the real patterns. So we can confirm the relation of interlayer visually from the real patterns. And we can verify interlayer design even during the fabrication process and conduct a non-destructive inspection. Also this methodology provides a large amount of measurement data. As previously stated, the statistical analysis of the extracted data enhances the degree of completeness and realizes the difference of process induced by different design environment. Through this methodology, we can calculate the margin of current interlayer design and suggest the requirement of design. And we will improve the interlayer design.