• Arthur:Yuriko Seino
  • Conference:SPIE2016
  • Company:EIDEC


In order to evaluate a directed self-assembly (DSA) technology for semiconductor device manufacturing, we developed a grapho- and chemohybrid coordinated line epitaxy (COOL) process, which requires neither special pinning guide materials nor resist strip process for sub-15 nm line and space (L/S) patterning by using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymers (BCPs); and we verified DSA process performances such as defects, local placement errors and pattern transfer [1,2]. Furthermore we fabricated half pitch (HP) 15 nm metal wire circuit using the COOL process and fully integrated it onto 300 mm wafers for an electrical yield test, which successfully revealed that meta wire circuits were electrically connected with the 700 ?m metal wire line length [3].

In a next stage, sub-10 nm L/S DSA patterning process, carried out by using grapho-epitaxial DSA [4] of lamellar organic BCPs and Si-containing BCPs, is investigated for the fabrication of sub-10 nm metal wire circuits. Figure 1 shows top-down SEM images of HP 10 nm L/S patterns using grapho-epitaxial DSA of lamellar organic BCPs, after a micro phase separation. Guides consisting of neutral layers of SiO2 and Si were formed in the heights of 30 nm (Figures 1 (a) and (b)) and 10 nm (Figure 1 (c)). HP 10 nm L/S patterns were formed in the guide spaces of about 2*L0 (lamellar period) and 3*L0. In this study, DSA patterning performance and pattern transfer will be reported. A part of this work was funded by the New Energy and Industrial Technology Development Organization (NEDO) under the EIDEC project.