SPIE Lithography Asia 2008
Jungchan Kim*a, Taehyeong Lee a, Areum Jung a, Gyun Yoo, Hyunjo Yang, Donggyu Yim a, Sungki Park a, Jaeyoung Seo b, Byoungjun Park b, Toshiaki Hasebe b, Masahiro Yamamoto b
a Memory Research & Development Division, Hynix Semiconductor Inc., Korea
b NGR Inc., Japan
The downscaling of the feature size and pitches of the semi-conductor device requires enough process window and good CDU of exposure field for improvement of device characteristics and high yield. Recently several DBMs (Design Based Metrologies) are introduced for the wafer verification and feed back to for DFM and process control. The major applications of DBM are OPC feed back, process window qualification and advanced process control feed back. With these tools, since the applied tool in this procedure uses e-beam scan method with database of design layout like other ones, more precise and quick verification can be done.
In this work the process window qualification procedure will be discussed in connection with EDA simulation results and then method for obtaining good CDU will be introduced. DoseMapperTM application has been introduced for better field CDU control, but it is difficult to fully correct large field with limited data from normal CD SEM methodology. New DBM has strong points in collecting lots of data required for large field correction with good repeatability (Intra / Inter field).