SPIE Lithography Asia 2008

Hyoung-Soon Yune, Yeong-Bae Ahn, Jung-Chan kim, Hye-Jin Shin, Gyun Yoo, James Moon, Byoung-Sub Nam, and Donggyu Yim

R&D Division, Hynix Semiconductor Inc.

San 136-1, Ami-ri, Bubal-eub, Ichon-si, Kyungki-do 467-701, Korea
Tel : 82-31-639-0871, Fax : 82-31-630-4546,
E-mail : hyoungsoon.yune@hynix.com

ABSTRACT

Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short. As the design rule is getting smaller, it becomes more difficult to accurately control critical dimension (CD) variation because of influence by nearby contact hole patterns. Especially, random contact hole shows greater amount of CD difference between X and Y direction compared to array contact holes. Several resolution enhancement techniques (RET) were used to resolve this kind of problem, but didn’t meet the overall expectations.

In this paper, we will present the results for novel contact hole model-based OPC for sub 60nm memory device. First, model calibration method will be proposed for contact hole patterns, which utilizes two thousands of real contact hole patterns to improve model accuracy in full chip. Second, verification method will be proposed to check weak points on full chip using model based verification. Finally, method for further enhancing CD variation within 5nm for model based OPC will be discussed using Die-to-Database Verification.