Shinji Yamaguchi, Eiji Yamanaka, *Hidefumi Mukai,*Toshiya Kotani, *Hiromitsu Mashita and Masamitsu Itoh
Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation
1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki, Japan
*Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation
8, Shinsugita-cho, Isogo-ku, Yokohama, Japan
The specification of photomask patterns is defined for each semiconductor device technology node based on the ITRS (International Technology Roadmap for Semiconductors). The quality of the photomask patterns has been managed by using a metrology tool for CD (Critical Dimension) and an inspection tool for pattern shape. According to shrinkage of semiconductor device patterns, the lithography margin has gradually become smaller. Consequently, the quality of photomask patterns has been managed by observing small lithography margin patterns in addition to the conventional quality management patterns with the conventional metrology tool. Furthermore, recently, as each successive device generation has become shorter, rapid improvement of not only turnaround time of photomask manufacturing but also yield of semiconductor device manufacturing has become necessary. Therefore, the importance of the flexible mask specifications concept is increasing. The quality of photomask patterns with respect to the specifications is judged in terms of pass/fail based on the allowable lithography margin . The methodology is that small lithography margin patterns are selected, micrographs of the selected photomask patterns are acquired by a metrology tool, photomask pattern contours are extracted with the micrographs, resist patterns exposed on Si wafer are simulated by using the photomask pattern contours with lithography simulation under actual exposure conditions, the lithography margin is calculated and the quality of the photomask is judged in terms of pass/fail criteria based on the lithography margin for each generation, device and layer.
For management of the quality of photomask patterns based on the flexible mask specifications, it is necessary to measure two-dimensional patterns such as hot-spot patterns for each critical layer in devices having small lithography margin. Therefore, in order to manage quality in the case of flexible mask specifications, a two-dimensional photomask pattern contour extraction tool was studied and developed . The photomask pattern contour extraction tool realizes the combination of acquisition of fine-pixel SEM (NGR4000) images of the photomask patterns in wide field and extraction of photomask pattern contours by using the acquired fine-pixel SEM images .
There have been many reports on the repeatability and reliability of CD and two-dimensional pattern metrology tools based on the conventional specifications. However, there are very few reports on the repeatability and reliability of photomask pattern metrology tools based on flexible mask specifications. In this paper, using small lithography margin patterns, firstly, the fine-pixel SEM images of photomask patterns are acquired. Secondly, contours of the photomask patterns are extracted with the SEM images. Thirdly, contours of resist patterns on Si wafer are simulated with lithography simulation under actual exposure condition by using the actual photomask pattern contours. Finally, the lithography margin is calculated by using FEM (Focus Exposure Matrix) for the simulated contours of resist patterns. This flow is repeated. The lithography margin with this flow is compared with that of actual exposed wafers. Repeatability and reliability of the lithography margin is evaluated. As a result, accuracy of the photomask pattern contour extraction tool is discussed.